A Compact AES Hardware Implementation Secure Against 1st-Order Side-Channel Attacks

Published in ICCD (36th IEEE International Conference on Computer Design), 2018

Citation: Qian Zhang, Yongbin Zhou, Shuang Qiu, Wei Cheng, Jingdian Ming, Rui Zhang. A Compact AES Hardware Implementation Secure Against 1st-Order Side-Channel Attacks. ICCD 2018 : 545-552. [Online link, Full version, BibTeX]

Efficient cryptographic implementations with desired side-channel attacks (SCA) resistance are highly required, especially for those resources-constrained devices. In this paper, we propose a very compact AES hardware implementation scheme provably secure against 1st-order SCAs. Basically, our scheme is inspired by ideas of Redundant Tower Field (RTF for short) circuit due to Ueno et al. and of private circuits due to Ishai, Sahai and Wagner (ISW for short), and is therefore named ISW-RTF. In terms of security, practical attacks on real leakages from prototype implementation show that ISW-RTF scheme is secure against 1st-order attacks and 2nd-order zero-offset attacks as well. Results of t-test leakage detection of these leakages also verify this observation. In terms of efficiency, compared with the state-of-the-art 1st-order masking scheme, our scheme outperforms at least 55.08% decreases in area, and 34.87% decreases in area-time product on three popular FPGA/ASIC devices. To the best of our knowledge, the proposed ISW-RTF scheme is the most compact one provably secure against SCA.